required to incorporate manufacturer-developed improvements and to
provide for other modification to the IDS. Design of processor
assemblies shall preclude user alteration of the integral firmware
and shall preclude use of the processor assemblies for purposes
other than the intended system and zone status monitoring,
control, and display.
(2) Unit design shall provide the capability for user-entered
time, date, and installation-related data such as sensor zone
numbers, zone descriptors, and control unit addresses. Design of
the memory in which user-entered data is stored shall ensure
storage of entered data for a minimum of 30 days in the absence of
power from external sources.
(3) Provide unit components of modular construction designed for
on-site equipment repair by module replacement.
(4) Unit shall be designed for minimum power consumption to
reduce required backup battery capacity.
(5) Unit shall switch automatically and instantaneously from ac
primary power to battery backup power on loss of ac primary power,
and from battery backup power to ac primary power on restoration
of ac primary power. Unit shall maintain the performance
specified herein during either change of power source.
(6) Unit power supplies shall fully recharge backup batteries
within 12 hours after restoration of ac primary power following no
more than 4 hours of system battery operation.
(7) Properly installed components shall exhibit intersystem and
intrasystem electromagnetic compatibility and shall not cause
performance degradation or malfunctions of other interconnected
electronic equipment with which the components interface.
**************************************************************************
NOTE: At the text below, RF signal communications
can only operate at a very low baud rate, 150 baud
or less. Confirm product sources before including
baud rates for RF data transmission.
**************************************************************************
c.
Processing: Unit shall operate in a continuous interrogation,
control, and response mode, using time-division-multiplex digital
communications techniques at a data rate of [5.12] [10.24] [_____]
kilobaud for central processor and control unit data flow.
Interrogation, control, and response communications between the
processor and control units shall be half-duplex, bidirectional on
one control unit bus, dual twisted pair cable (one pair for
interrogation, one for response) which may have one or more
parallel branches. Individual data bus lines shall be 22 AWG or
larger wire. Connect control units parallel to the bus. The
central processor shall provide for the connection of at least
[127] [_____] control units to the bus. Processor shall operate
in a continuous mode, using time-division-multiplex digital
communications techniques at a data rate of [10.24] [_____]
kilobaud for central processor to fixed and CRT map display data
flow. Communications between central processor and map displays
shall be simplex, unidirectional on one map bus single twisted
SECTION 13703N
Page 59
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